On modeling of Chip Interconnects. Boolchandani, D. & Sahula, V. In IETE Annual Zonal seminar on Electronic Design Automation: Issues & Challenges, Jaipur, May, 2003. Paper bibtex @inproceedings{
title = {On modeling of Chip Interconnects},
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author = {Boolchandani, D and Sahula, V},
booktitle = {IETE Annual Zonal seminar on Electronic Design Automation: Issues & Challenges, Jaipur, May}
}
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