Estimation methods for static noise margins in CMOS subthreshold logic circuits. Bortolon, F. T., Moraes, F. G., Moreira, M. T., & Bampi, S. In Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017, pages 90–95, 2017. ACM.
Estimation methods for static noise margins in CMOS subthreshold logic circuits [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/sbcci/BortolonMMB17,
  author    = {Felipe T. Bortolon and
               Fernando Gehm Moraes and
               Matheus T. Moreira and
               Sergio Bampi},
  editor    = {Jarbas A. N. Silveira},
  title     = {Estimation methods for static noise margins in {CMOS} subthreshold
               logic circuits},
  booktitle = {Proceedings of the 30th Symposium on Integrated Circuits and Systems
               Design: Chip on the Sands, {SBCCI} 2017, Fortaleza, Cear{\'{a}}, Brazil,
               August 28 - September 01, 2017},
  pages     = {90--95},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3109984.3109998},
  doi       = {10.1145/3109984.3109998},
  timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/sbcci/BortolonMMB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Downloads: 0