Tolerating Hard Faults in Microprocessor Array Structures. Bower, F. A., Shealy, P. G., Ozev, S., & Sorin, D. J. In DSN, pages 51-60, 2004. IEEE Computer Society.
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Paper bibtex @inproceedings{conf/dsn/BowerSOS04,
added-at = {2023-03-24T00:00:00.000+0100},
author = {Bower, Fred A. and Shealy, Paul G. and Ozev, Sule and Sorin, Daniel J.},
biburl = {https://www.bibsonomy.org/bibtex/2886877a32a0988794c553125057ebf88/dblp},
booktitle = {DSN},
crossref = {conf/dsn/2004},
ee = {https://doi.ieeecomputersociety.org/10.1109/DSN.2004.1311876},
interhash = {6465b64e8cf50874282d3e44049585ea},
intrahash = {886877a32a0988794c553125057ebf88},
isbn = {0-7695-2052-9},
keywords = {dblp},
pages = {51-60},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T16:06:01.000+0200},
title = {Tolerating Hard Faults in Microprocessor Array Structures.},
url = {http://dblp.uni-trier.de/db/conf/dsn/dsn2004.html#BowerSOS04},
year = 2004
}
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