Étude et implémentation d’une méthode de calcul pour la simulation numérique sur des architectures modernes. Cassagne, A. Master's thesis, EPSI Bordeaux, 2015. ![Étude et implémentation d’une méthode de calcul pour la simulation numérique sur des architectures modernes [pdf]](https://bibbase.org/img/filetypes/pdf.svg "pdf")
Paper abstract bibtex 4 downloads In this thesis we will study some modern hardware architectures using a well-known method in digital simulation: the stencil codes. The current HPC context is quite suitable for the arrival of new technologies leaded by the race to exascale computation. The comparative analysis in this thesis is mainly based on performance (number of floating point operations per second) and on hardware energy efficiency. We will start by formalising and clarifing the stencil method, then we will take a deeper look at three architectures : one standard x86 CPU, one low consumption ARM CPU and one GPU specialized in computations. Thereafter, we will describe some stencil optimisations in order to implement efficient versions of code for each of the architectures. We will explore both well-known methods like Cache Blocking and Register Blocking as well as less known ones such as Dimension Lifted and Transposed and Temporal Blocking. To finish, all these implementations will be tested on a low order stencil using the heat equation discretisation. The analysis will contain three different parts following the three architectures. We will use the Roofline model in order to bound the maximal reachable performance. Then we will study the code internal behavior on CPU and GPU by modifying the problem size. We will also take a look on the weak scalability in caches but only for the CPUs. Lastly, we will present a comparative analysis of energy consumption (also called energy to solution analysis).
@MastersThesis{Cassagne2015b,
author = {A. Cassagne},
title = {Étude et implémentation d’une méthode de calcul pour la simulation numérique sur des architectures modernes},
school = {EPSI Bordeaux},
year = {2015},
abstract = {In this thesis we will study some modern hardware architectures using a well-known method in digital simulation: the stencil codes. The current HPC context is quite suitable for the arrival of new technologies leaded by the race to exascale computation. The comparative analysis in this thesis is mainly based on performance (number of floating point operations per second) and on hardware energy efficiency. We will start by formalising and clarifing the stencil method, then we will take a deeper look at three architectures : one standard x86 CPU, one low consumption ARM CPU and one GPU specialized in computations. Thereafter, we will describe some stencil optimisations in order to implement efficient versions of code for each of the architectures. We will explore both well-known methods like Cache Blocking and Register Blocking as well as less known ones such as Dimension Lifted and Transposed and Temporal Blocking. To finish, all these implementations will be tested on a low order stencil using the heat equation discretisation. The analysis will contain three different parts following the three architectures. We will use the Roofline model in order to bound the maximal reachable performance. Then we will study the code internal behavior on CPU and GPU by modifying the problem size. We will also take a look on the weak scalability in caches but only for the CPUs. Lastly, we will present a comparative analysis of energy consumption (also called energy to solution analysis).},
url_Paper = {https://largo.lip6.fr/~cassagnea/docs/reports/Cassagne2015b%20-%20Etude%20et%20implementation%20d%20une%20methode%20de%20calcul%20pour%20la%20simulation%20numerique%20sur%20des%20architectures%20modernes.pdf},
}
Downloads: 4
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