Timed Games for Computing WCET for Pipelined Processors with Caches. Cassez, F. In 11th International Conference on Application of Concurrency to System Design, ACSD 2011, Newcastle Upon Tyne, UK, 20-24 June, 2011, pages 195–204, 2011. IEEE.
Timed Games for Computing WCET for Pipelined Processors with Caches [pdf]Paper  Timed Games for Computing WCET for Pipelined Processors with Caches [pdf]Slides  Timed Games for Computing WCET for Pipelined Processors with Caches [link]Link  doi  abstract   bibtex   
In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game. We demonstrate the applicability of our framework on standard benchmarks for an ARM9 processor with instruction and data caches, and compute the WCET with UPPAAL-TiGA. We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution.

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