Timed Games for Computing Worst-Case Execution-Times. Cassez, F. CoRR, 2010.
Timed Games for Computing Worst-Case Execution-Times [link]Paper  abstract   bibtex   
In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game. We demonstrate the applicability of our framework on standard benchmarks for an ARM9 processor with instruction and data caches, and compute the WCET with UPPAAL-TiGA. We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution.
@article{DBLP:journals/corr/abs-1006-1951,
  author    = {Franck Cassez},
  title     = {Timed Games for Computing Worst-Case Execution-Times},
  journal   = {CoRR},
  Type = {E - Reports},
  volume    = {abs/1006.1951},
  year      = {2010},
  url       = {http://arxiv.org/abs/1006.1951},
  timestamp = {Mon, 05 Dec 2011 18:04:54 +0100},
  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/abs-1006-1951},
  bibsource = {dblp computer science bibliography, http://dblp.org},
    keywords = {wcet, timed automata},

  abstract= {In this paper we introduce a framework for computing upper bounds yet accurate WCET for hardware platforms with caches and pipelines. The methodology we propose consists of 3 steps: 1) given a program to analyse, compute an equivalent (WCET-wise) abstract program; 2) build a timed game by composing this abstract program with a network of timed automata modeling the architecture; and 3) compute the WCET as the optimal time to reach a winning state in this game. We demonstrate the applicability of our framework on standard benchmarks for an ARM9 processor with instruction and data caches, and compute the WCET with UPPAAL-TiGA. We also show that this framework can easily be extended to take into account dynamic changes in the speed of the processor during program execution.}
}


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