Formal Verification of Finite State Machines. Chandran, U., Kuldeep, D., & Sahula, V. In 6th IEEE VLSI Design and Test Workshops, 2002.
bibtex   
@inproceedings{
 title = {Formal Verification of Finite State Machines},
 type = {inproceedings},
 year = {2002},
 id = {b2ac60e3-cb9e-39bb-8191-d031b395195e},
 created = {2014-04-17T21:17:22.000Z},
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 last_modified = {2017-03-14T01:22:09.162Z},
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 citation_key = {u2002formal},
 source_type = {inproceedings},
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 bibtype = {inproceedings},
 author = {Chandran, U and Kuldeep, D and Sahula, V},
 booktitle = {6th IEEE VLSI Design and Test Workshops}
}

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