Accurate performance evaluation of VLSI designs with selected CMOS process parameters. Chang, C. L. & Wen, C. H. IET Circuits Devices Syst., 12(1):116-123, 2018.
Accurate performance evaluation of VLSI designs with selected CMOS process parameters. [link]Link  Accurate performance evaluation of VLSI designs with selected CMOS process parameters. [link]Paper  bibtex   
@article{journals/iet-cds/ChangW18,
  added-at = {2020-09-10T00:00:00.000+0200},
  author = {Chang, Chia-Ling Lynn and Wen, Charles H.-P.},
  biburl = {https://www.bibsonomy.org/bibtex/2ef97006e35c511a69daf6fddcbf78abb/dblp},
  ee = {https://doi.org/10.1049/iet-cds.2017.0097},
  interhash = {14870dab20e7a81faea552b7c06b66cb},
  intrahash = {ef97006e35c511a69daf6fddcbf78abb},
  journal = {IET Circuits Devices Syst.},
  keywords = {dblp},
  number = 1,
  pages = {116-123},
  timestamp = {2020-09-11T11:44:15.000+0200},
  title = {Accurate performance evaluation of VLSI designs with selected CMOS process parameters.},
  url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds12.html#ChangW18},
  volume = 12,
  year = 2018
}

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