On the feasibility of CMOS multiband phase shifters for multiple-antenna transmitters. Chao Lu, Pham, A., -., H., & Livezey, D. IEEE Microwave and Wireless Components Letters, 16(5):255-257, 5, 2006.
abstract   bibtex   
We present the design of an integrated multiband phase shifter in RF CMOS technology for phased array transmitters. The phase shifter has an embedded classical distributed amplifier for loss compensation. The phase shifter achieves a more than 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured more than 360/spl deg/ phase tuning range in both 3.5-GHz and 5.8-GHz bands. The return loss is less than -10dB at all conditions. The feasibility for transmitter applications is verified through measurements. The output power at a 1-dB compression point (P/sub 1 dB/) is as high as 0.4dBmat 2.4GHz. The relative phase deviation around P/sub 1 dB/ is less than 3/spl deg/. The design is implemented in 0.18-μmRF CMOS technology, and the chip size is 1200μm × 2300 μm including pads.
@article{
 title = {On the feasibility of CMOS multiband phase shifters for multiple-antenna transmitters},
 type = {article},
 year = {2006},
 identifiers = {[object Object]},
 keywords = {radio transmitters;transmitting antennas;antenna p},
 pages = {255-257},
 volume = {16},
 month = {5},
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 abstract = {We present the design of an integrated multiband phase shifter in RF CMOS technology for phased array transmitters. The phase shifter has an embedded classical distributed amplifier for loss compensation. The phase shifter achieves a more than 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured more than 360/spl deg/ phase tuning range in both 3.5-GHz and 5.8-GHz bands. The return loss is less than -10dB at all conditions. The feasibility for transmitter applications is verified through measurements. The output power at a 1-dB compression point (P/sub 1 dB/) is as high as 0.4dBmat 2.4GHz. The relative phase deviation around P/sub 1 dB/ is less than 3/spl deg/. The design is implemented in 0.18-μmRF CMOS technology, and the chip size is 1200μm × 2300 μm including pads.},
 bibtype = {article},
 author = {Chao Lu, undefined and Pham, A -. H and Livezey, D},
 journal = {IEEE Microwave and Wireless Components Letters},
 number = {5}
}
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