A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. Chen, G. K., Anders, M., Kaul, H., Satpathy, S., Mathew, S. K., Hsu, S., Agarwal, A., Krishnamurthy, R., De, V., & Borkar, S. Y. J. Solid-State Circuits, 50(1):59-67, 2015.

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@article{journals/jssc/ChenAKSMHAKDB15,
  added-at = {2015-01-08T00:00:00.000+0100},
  author = {Chen, Gregory K. and Anders, Mark and Kaul, Himanshu and Satpathy, Sudhir and Mathew, Sanu K. and Hsu, Steven and Agarwal, Amit and Krishnamurthy, Ram and De, Vivek and Borkar, Shekhar Y.},
  biburl = {http://www.bibsonomy.org/bibtex/2600472ee6963ffd29780abb88b606fee/dblp},
  ee = {http://dx.doi.org/10.1109/JSSC.2014.2369508},
  interhash = {3753980feae4a07ffb4aeefdca7caa1a},
  intrahash = {600472ee6963ffd29780abb88b606fee},
  journal = {J. Solid-State Circuits},
  keywords = {dblp},
  number = 1,
  pages = {59-67},
  timestamp = {2015-06-18T06:57:20.000+0200},
  title = {A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.},
  url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#ChenAKSMHAKDB15},
  volume = 50,
  year = 2015
}

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