A 16 nm 128 Mb SRAM in High- $ąppa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. Chen, Y., Chan, W., Wu, W., Liao, H., Pan, K., Liaw, J., Chung, T., Li, Q., Lin, C., Chiang, M., Wu, S., & Chang, J. J. Solid-State Circuits, 50(1):170-177, 2015.
A 16 nm 128 Mb SRAM in High- $ąppa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. [link]Link  A 16 nm 128 Mb SRAM in High- $ąppa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications. [link]Paper  bibtex   
@article{journals/jssc/ChenCWLPLCLLCWC15,
  added-at = {2015-01-08T00:00:00.000+0100},
  author = {Chen, Yen-Huei and Chan, Wei-Min and Wu, Wei-Cheng and Liao, Hung-Jen and Pan, Kuo-Hua and Liaw, Jhon-Jhy and Chung, Tang-Hsuan and Li, Quincy and Lin, Chih-Yung and Chiang, Mu-Chi and Wu, Shien-Yang and Chang, Jonathan},
  biburl = {http://www.bibsonomy.org/bibtex/23ccda6925b333fb5857d281f9c154aa6/dblp},
  ee = {http://dx.doi.org/10.1109/JSSC.2014.2349977},
  interhash = {8863cf952918c80499e55c4058e08440},
  intrahash = {3ccda6925b333fb5857d281f9c154aa6},
  journal = {J. Solid-State Circuits},
  keywords = {dblp},
  number = 1,
  pages = {170-177},
  timestamp = {2015-06-18T06:57:03.000+0200},
  title = {A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.},
  url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#ChenCWLPLCLLCWC15},
  volume = 50,
  year = 2015
}

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