Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. Chen, Y., Li, H., Koh, C., Sun, G., Li, J., Xie, Y., & Roy, K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(11):1621–1624, Nov, 2010.
doi bibtex

@ARTICLE{chen2010tvlsi, 
author={Yiran Chen and Hai Li and Cheng-Kok Koh and Guangyu Sun and Jing Li and Yuan Xie and Kaushik Roy}, 
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 
title={Variable-Latency Adder ({VL-Adder}) Designs for Low Power and {NBTI} Tolerance}, 
year={2010}, 
volume={18}, 
number={11}, 
pages={1621--1624}, 
keywords={journal, adders,digital arithmetic,integrated circuit design,logic design,IC design,NBTI tolerance,circuit delay,digital arithmetic,logic design,negative bias temperature instability,variable-latency adder designs,word length 64 bit,Adders,Circuits,Clocks,Delay,Negative bias temperature instability,Niobium compounds,Sun,Throughput,Titanium compounds,Very large scale integration,Digital arithmetic,IC design,logic design}, 
doi={10.1109/TVLSI.2009.2026280}, 
ISSN={1063-8210}, 
month={Nov},
}

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