Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. Chen, Y., Li, H., Li, J., & Koh, C. In 2007 ACM/IEEE International Symposium on Low Power Electronics and Design (<strong>ISLPED</strong>), pages 195–200, Aug, 2007.
doi bibtex

@INPROCEEDINGS{li2007islped, 
author={Yiran Chen and Hai Li and Jing Li and Cheng-Kok Koh}, 
booktitle={2007 ACM/IEEE International Symposium on Low Power Electronics and Design (<strong>ISLPED</strong>)}, 
title={Variable-latency adder ({VL-adder}): new arithmetic circuit design practice to overcome {NBTI}}, 
year={2007}, 
volume={}, 
number={}, 
pages={195--200}, 
keywords={conference, MOSFET,adders,logic design,low-power electronics,NBTI-induced delay degradation,NBTI-tolerant techniques,VL-adder,arithmetic circuit design,clock edge,energy efficiency,lower-power adder designs,manufacturing costs,nanoscale PMOS transistors,negative bias temperature instability,variable-latency adder technique,Adders,Arithmetic,Circuit synthesis,Clocks,Degradation,Delay,MOSFETs,Negative bias temperature instability,Niobium compounds,Titanium compounds,negative bias temperature instability (NBTI),variable-latency adder (VL-adder)}, 
doi={10.1145/1283780.1283822}, 
ISSN={}, 
month={Aug},
%note = {(Acceptance Rate: <u>39\%</u>, 74 out of 192)},
}

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