Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). Cheng, E., Mirkhani, S., Szafaryn, L. G., Cher, C., Cho, H., Skadron, K., Stan, M. R., Lilja, K., Abraham, J. A., Bose, P., & Mitra, S. IEEE transactions on computer-aided design of integrated circuits and systems, 2018.
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) [link]Paper  bibtex   
@article{2608,
  author = {Eric Cheng and Shahrzad Mirkhani and Lukasz G. Szafaryn and Chen-Yong Cher and Hyungmin Cho and Kevin Skadron and Mircea R. Stan and K. Lilja and Jacob A. Abraham and Pradip Bose and Subhasish Mitra},
  title = {Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)},
  year = {2018},
  journal = {IEEE transactions on computer-aided design of integrated circuits and systems},
  url = {https://doi.org/10.1109/tcad.2017.2752705}
}

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