A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. Chiu, P., Liu, M., Tang, Q., & Kim, C. H. In A-SSCC, pages 187-190, 2018. IEEE.
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. [link]Link  A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. [link]Paper  bibtex   
@inproceedings{conf/asscc/ChiuLTK18,
  added-at = {2019-01-07T00:00:00.000+0100},
  author = {Chiu, Po-Wei and Liu, Muqing and Tang, Qianying and Kim, Chris H.},
  biburl = {https://www.bibsonomy.org/bibtex/22222f14cb4f9fc132b46d2f084144689/dblp},
  booktitle = {A-SSCC},
  crossref = {conf/asscc/2018},
  ee = {https://doi.org/10.1109/ASSCC.2018.8579267},
  interhash = {83b1db6daa339b45a457a470d57e03b4},
  intrahash = {2222f14cb4f9fc132b46d2f084144689},
  isbn = {978-1-5386-6413-1},
  keywords = {dblp},
  pages = {187-190},
  publisher = {IEEE},
  timestamp = {2019-01-08T11:43:30.000+0100},
  title = {A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer.},
  url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2018.html#ChiuLTK18},
  year = 2018
}

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