A Traffic Model for Concurrent Core Tasks in Networks-on-Chip. Chuggani, R., Laxmi, V., Gaur, M. S., Khandelwal, P., & Bansal, P. In Sixth IEEE International Symposium on Electronic Design, Test and Application, DELTA 2011, Queenstown, New Zealand, 17-19 January, 2011, pages 205–210, 2011. Paper doi bibtex @inproceedings{DBLP:conf/delta/ChugganiLGKB11,
author = {Roopesh Chuggani and
Vijay Laxmi and
Manoj Singh Gaur and
Pankaj Khandelwal and
Prateek Bansal},
title = {A Traffic Model for Concurrent Core Tasks in Networks-on-Chip},
booktitle = {Sixth {IEEE} International Symposium on Electronic Design, Test and
Application, {DELTA} 2011, Queenstown, New Zealand, 17-19 January,
2011},
pages = {205--210},
year = {2011},
crossref = {DBLP:conf/delta/2011},
url = {https://doi.org/10.1109/DELTA.2011.45},
doi = {10.1109/DELTA.2011.45},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/delta/ChugganiLGKB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
Downloads: 0
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