Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. Ciesielski, M. J., Kalla, P., & Askar, S. IEEE Trans. Computers, 55(9):1188–1201, 2006. Paper doi bibtex @article{DBLP:journals/tc/CiesielskiKA06,
author = {Maciej J. Ciesielski and
Priyank Kalla and
Serkan Askar},
title = {Taylor Expansion Diagrams: {A} Canonical Representation for Verification
of Data Flow Designs},
journal = {{IEEE} Trans. Computers},
volume = {55},
number = {9},
pages = {1188--1201},
year = {2006},
url = {https://doi.org/10.1109/TC.2006.153},
doi = {10.1109/TC.2006.153},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/bib/journals/tc/CiesielskiKA06},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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