Digraph Relaxation for 2-Dimensional Placement of IC Blocks. Ciesielski, M. J. & Kinnen, E. IEEE Trans. on CAD of Integrated Circuits and Systems, 6(1):55-66, 1987.
Link
Paper bibtex @article{journals/tcad/CiesielskiK87,
added-at = {2012-02-24T00:00:00.000+0100},
author = {Ciesielski, Maciej J. and Kinnen, Edwin},
biburl = {https://www.bibsonomy.org/bibtex/2e4e690ca648ee7c47b9841b8529ffc4a/dblp},
ee = {http://dx.doi.org/10.1109/TCAD.1987.1270246},
interhash = {593359bae52deb5fb013896739fa2c6d},
intrahash = {e4e690ca648ee7c47b9841b8529ffc4a},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
keywords = {dblp},
number = 1,
pages = {55-66},
timestamp = {2012-02-28T11:34:58.000+0100},
title = {Digraph Relaxation for 2-Dimensional Placement of IC Blocks.},
url = {http://dblp.uni-trier.de/db/journals/tcad/tcad6.html#CiesielskiK87},
volume = 6,
year = 1987
}