@inproceedings{DBLP:conf/dsd/DehbashiFRR12,
  author    = {Mehdi Dehbashi and
               G{\"{o}}rschwin Fey and
               Kaushik Roy and
               Anand Raghunathan},
  title     = {On Modeling and Evaluation of Logic Circuits under Timing Variations},
  booktitle = {15th Euromicro Conference on Digital System Design, {DSD} 2012, Cesme,
               Izmir, Turkey, September 5-8, 2012},
  pages     = {431--436},
  year      = {2012},
  crossref  = {DBLP:conf/dsd/2012},
  url       = {https://doi.org/10.1109/DSD.2012.91},
  doi       = {10.1109/DSD.2012.91},
  timestamp = {Fri, 02 Jun 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dsd/DehbashiFRR12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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