Stochastic Automata Network for Performance Evaluation of Heterogeneous SoC Communication. Deshmukh, U. & Sahula, V. In Norchip - 26th Norchip Conference, Formal Proceedings, pages 208-211, 11, 2008. IEEE.
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Paper Website doi abstract bibtex To meet ever increasing demand for performance of emerging System-on-Chip (SoC) applications, designer employ techniques for concurrent communication between components. Hence communication architecture becomes complex and major performance bottleneck. An early performance evaluation of communication architecture is the key to reduce design time, time-to-market and consequently cost of the system. Moreover, it helps to optimize system performance by selecting appropriate communication architecture. However, performance model of concurrent communication is complex to describe and hard to solve. In this paper, we propose methodology for performance evaluation of bus based communication architectures, modeling for which is based on modular Stochastic Automata Network (SAN). We employ Generalized Semi Markov Process (GSMP) model for each module of the SAN that emulates dynamic behavior of a Processing Element (PE) of an SoC architecture. The proposed modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element; while we provide parameters viz. number of processing elements, the mean computation time of processing elements and the first and second moments of connection time between processing elements and memories, as input to the model.
@inproceedings{
title = {Stochastic Automata Network for Performance Evaluation of Heterogeneous SoC Communication},
type = {inproceedings},
year = {2008},
keywords = {Automata,Computer architecture,Costs,GSMP model,Markov processes,Parameter estimation,Stochastic processes,Storage area networks,System performance,System-on-a-chip,Time to market,bus based communication architecture,generalized semi Markov process,heterogeneous SoC communication,memory bandwidth,modular SAN,parameter estimation,performance evaluation,processing element,queue length,queueing theory,stochastic automata,stochastic automata network,system buses,system-on-chip},
pages = {208-211},
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month = {11},
publisher = {IEEE},
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abstract = {To meet ever increasing demand for performance of emerging System-on-Chip (SoC) applications, designer employ techniques for concurrent communication between components. Hence communication architecture becomes complex and major performance bottleneck. An early performance evaluation of communication architecture is the key to reduce design time, time-to-market and consequently cost of the system. Moreover, it helps to optimize system performance by selecting appropriate communication architecture. However, performance model of concurrent communication is complex to describe and hard to solve. In this paper, we propose methodology for performance evaluation of bus based communication architectures, modeling for which is based on modular Stochastic Automata Network (SAN). We employ Generalized Semi Markov Process (GSMP) model for each module of the SAN that emulates dynamic behavior of a Processing Element (PE) of an SoC architecture. The proposed modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element; while we provide parameters viz. number of processing elements, the mean computation time of processing elements and the first and second moments of connection time between processing elements and memories, as input to the model.},
bibtype = {inproceedings},
author = {Deshmukh, Ulhas and Sahula, Vineet},
doi = {10.1109/NORCHP.2008.4738313},
booktitle = {Norchip - 26th Norchip Conference, Formal Proceedings}
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