DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. Deutsch, S., Keller, B. L., Chickermane, V., Mukherjee, S., Sood, N., Goel, S. K., Chen, J., Mehta, A., Lee, F., & Marinissen, E. J. In ITC, pages 1-10, 2012. IEEE Computer Society. Link Paper bibtex @inproceedings{conf/itc/DeutschKCMSGCMLM12,
added-at = {2015-08-26T00:00:00.000+0200},
author = {Deutsch, Sergej and Keller, Brion L. and Chickermane, Vivek and Mukherjee, Subhasish and Sood, Navdeep and Goel, Sandeep Kumar and Chen, Ji-Jan and Mehta, Ashok and Lee, Frank and Marinissen, Erik Jan},
biburl = {http://www.bibsonomy.org/bibtex/203708a647811e6a4d485cf3fde249482/dblp},
booktitle = {ITC},
crossref = {conf/itc/2012},
ee = {http://doi.ieeecomputersociety.org/10.1109/TEST.2012.6401569},
interhash = {ba26ea81e5cefeaae45a0a604777ca3e},
intrahash = {03708a647811e6a4d485cf3fde249482},
isbn = {978-1-4673-1594-4},
keywords = {dblp},
pages = {1-10},
publisher = {IEEE Computer Society},
timestamp = {2015-08-29T11:47:15.000+0200},
title = {DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.},
url = {http://dblp.uni-trier.de/db/conf/itc/itc2012.html#DeutschKCMSGCMLM12},
year = 2012
}
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