@inproceedings{conf/cicc/DhongGKYLHWH14,
  added-at = {2014-11-15T00:00:00.000+0100},
  author = {Dhong, Sang H. and Guo, Richard and Kuo, Ming-Zhang and Yang, Ping-Lin and Lin, Cheng-Chung and Huang, Kevin and Wang, Min-Jer and Hwang, Wei},
  biburl = {https://www.bibsonomy.org/bibtex/22a9d695ac40dbc435dfc0000b0063e34/dblp},
  booktitle = {CICC},
  crossref = {conf/cicc/2014},
  ee = {http://dx.doi.org/10.1109/CICC.2014.6946044},
  interhash = {d453d8da0fb3f0620f717211127ea722},
  intrahash = {2a9d695ac40dbc435dfc0000b0063e34},
  keywords = {dblp},
  pages = {1-4},
  publisher = {IEEE},
  timestamp = {2015-06-18T19:51:13.000+0200},
  title = {A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.},
  url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2014.html#DhongGKYLHWH14},
  year = 2014
}

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