Electrical Transport at Room and Low Temperature in 3D Vertically Stacked SiGe and SiGeC Nanowires. Diab, A., Saracco, E., Ionica, I., Bonafos, C., Damlencourt, J. F., Lee, J., & Cristoloveanu, S. Journal of the Electrochemical Society, 159(4):H467--H472, 2012.
doi  abstract   bibtex   
In order to improve device performance, recent trends in microelectronics are to explore nanowire gate-all-around structures and alternative channel materials with superior properties. In this paper, we investigate the electrical transport properties, at room and low temperature, in as-grown three-dimensional (3D) vertically stacked germanium (Ge)-enriched nanowires. Measurements using the Pseudo-MOSFET (Psi-MOSFET) concept show that the transport in gateless nanowires is controlled by the voltage applied on the substrate, as in a MOS transistor. Interestingly, the substrate bias effect depends on the designed geometry of the nanowire. In nanowires with high width/length aspect ratio, we show the possibility of turning on both electron and hole channels. For nanowires with small width/length ratio, only the hole channel is visible. The impact of series resistance on the drain current level is reported. Transport modification with the concentration of germanium in the nanostructures is also discussed. Low-temperature measurements show the variation of electrical parameters such as threshold voltage, flatband voltage, subthreshold swing and mobility. The transport properties in multi-parallel stacked nanowire are addressed. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.005205jes] All rights reserved.
@article{ diab_electrical_2012,
  title = {Electrical Transport at Room and Low Temperature in {3D} Vertically Stacked {SiGe} and {SiGeC} Nanowires},
  volume = {159},
  issn = {0013-4651},
  doi = {10.1149/2.005205jes},
  abstract = {In order to improve device performance, recent trends in microelectronics are to explore nanowire gate-all-around structures and alternative channel materials with superior properties. In this paper, we investigate the electrical transport properties, at room and low temperature, in as-grown three-dimensional ({3D)} vertically stacked germanium (Ge)-enriched nanowires. Measurements using the Pseudo-{MOSFET} (Psi-{MOSFET)} concept show that the transport in gateless nanowires is controlled by the voltage applied on the substrate, as in a {MOS} transistor. Interestingly, the substrate bias effect depends on the designed geometry of the nanowire. In nanowires with high width/length aspect ratio, we show the possibility of turning on both electron and hole channels. For nanowires with small width/length ratio, only the hole channel is visible. The impact of series resistance on the drain current level is reported. Transport modification with the concentration of germanium in the nanostructures is also discussed. Low-temperature measurements show the variation of electrical parameters such as threshold voltage, flatband voltage, subthreshold swing and mobility. The transport properties in multi-parallel stacked nanowire are addressed. (C) 2012 The Electrochemical Society. [{DOI:} 10.1149/2.005205jes] All rights reserved.},
  language = {English},
  number = {4},
  journal = {Journal of the Electrochemical Society},
  author = {Diab, A. and Saracco, E. and Ionica, I. and Bonafos, C. and Damlencourt, J. F. and Lee, J.-H. and Cristoloveanu, S.},
  year = {2012},
  keywords = {devices, mobility, operation, parameter extraction, performance, transistors, wafers},
  pages = {H467--H472}
}

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