ASIC BIST Synthesis: A VHDL Approach. Eberle, T., McVay, R., Meyers, C., & Moore, J. In ITC, pages 741-750, 1996. IEEE Computer Society.
ASIC BIST Synthesis: A VHDL Approach. [link]Link  ASIC BIST Synthesis: A VHDL Approach. [link]Paper  bibtex   
@inproceedings{ conf/itc/EberleMMM96,
  added-at = {2012-02-08T00:00:00.000+0100},
  author = {Eberle, Tom and McVay, Robert and Meyers, Chris and Moore, Jason},
  biburl = {http://www.bibsonomy.org/bibtex/2cf3dc8b08b8356e1d916302887364b49/dblp},
  booktitle = {ITC},
  crossref = {conf/itc/1996},
  ee = {http://doi.ieeecomputersociety.org/10.1109/TEST.1996.557133},
  interhash = {f3a61640c012904c16102f653f5ca17e},
  intrahash = {cf3dc8b08b8356e1d916302887364b49},
  isbn = {0-7803-3541-4},
  keywords = {dblp},
  pages = {741-750},
  publisher = {IEEE Computer Society},
  title = {ASIC BIST Synthesis: A VHDL Approach.},
  url = {http://dblp.uni-trier.de/db/conf/itc/itc1996.html#EberleMMM96},
  year = {1996}
}

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