Post-synthesis back-annotation of timing information in behavioral VHDL. Eles, P., Kuchcinski, K., Peng, Z., & Doboli, A. Journal of Systems Architecture, 42(9-10):725-741, 1997.
Post-synthesis back-annotation of timing information in behavioral VHDL. [link]Link  Post-synthesis back-annotation of timing information in behavioral VHDL. [link]Paper  bibtex   
@article{ journals/jsa/ElesKPD97,
  added-at = {2009-09-17T00:00:00.000+0200},
  author = {Eles, Petru and Kuchcinski, Krzysztof and Peng, Zebo and Doboli, Alexa},
  biburl = {http://www.bibsonomy.org/bibtex/28113aa6eadf316483854f7f59f96b0ed/dblp},
  date = {2009-09-17},
  description = {dblp},
  ee = {http://dx.doi.org/10.1016/S1383-7621(96)00073-2},
  interhash = {536b9661300a6cf8a4666b6443b58a9e},
  intrahash = {8113aa6eadf316483854f7f59f96b0ed},
  journal = {Journal of Systems Architecture},
  keywords = {dblp},
  number = {9-10},
  pages = {725-741},
  title = {Post-synthesis back-annotation of timing information in behavioral VHDL.},
  url = {http://dblp.uni-trier.de/db/journals/jsa/jsa42.html#ElesKPD97},
  volume = {42},
  year = {1997}
}

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