Timing constraint specification and synthesis in behavioral VHDL. Eles, P., Kuchcinski, K., Peng, Z., & Doboli, A. In EURO-DAC, pages 452-457, 1995. IEEE Computer Society.
Timing constraint specification and synthesis in behavioral VHDL. [link]Link  Timing constraint specification and synthesis in behavioral VHDL. [link]Paper  bibtex   
@inproceedings{ conf/eurodac/ElesKPD95,
  added-at = {2008-04-09T00:00:00.000+0200},
  author = {Eles, Petru and Kuchcinski, Krzysztof and Peng, Zebo and Doboli, Alexa},
  biburl = {http://www.bibsonomy.org/bibtex/25ac1af06ed0d0742d896f20c8fe594f1/dblp},
  booktitle = {EURO-DAC},
  crossref = {conf/eurodac/1995},
  date = {2008-04-09},
  description = {dblp},
  ee = {http://doi.acm.org/10.1145/224270.224369},
  interhash = {dafdfd74aa810146703c2fb6ab0414e4},
  intrahash = {5ac1af06ed0d0742d896f20c8fe594f1},
  isbn = {0-8186-7156-4},
  keywords = {dblp},
  pages = {452-457},
  publisher = {IEEE Computer Society},
  title = {Timing constraint specification and synthesis in behavioral VHDL.},
  url = {http://dblp.uni-trier.de/db/conf/eurodac/euro-dac1995.html#ElesKPD95},
  year = {1995}
}

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