Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. Espasa, R. & Valero, M. In Proceedings of High Performance Computing (HiPC), pages 350-357, 1997.
Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance [link]Paper  bibtex   
@inproceedings{ dblp4425187,
  title = {Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance},
  author = {Roger Espasa and Mateo Valero},
  author_short = {Espasa, R. and Valero, M.},
  bibtype = {inproceedings},
  type = {inproceedings},
  year = {1997},
  key = {dblp4425187},
  id = {dblp4425187},
  biburl = {http://www.dblp.org/rec/bibtex/conf/hipc/EspasaV97},
  url = {http://doi.ieeecomputersociety.org/10.1109/HIPC.1997.634514},
  conference = {HiPC},
  pages = {350-357},
  text = {HiPC 1997:350-357},
  booktitle = {Proceedings of High Performance Computing (HiPC)}
}

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