Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. Esseni, D., Guglielmini, M., Kapidani, B., Rollo, T., & Alioto, M. IEEE Trans. VLSI Syst., 22(12):2488-2498, 2014.
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. [link]Link  Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. [link]Paper  bibtex   
@article{ journals/tvlsi/EsseniGKRA14,
  added-at = {2014-12-01T00:00:00.000+0100},
  author = {Esseni, David and Guglielmini, Manuel and Kapidani, Bernard and Rollo, Tommaso and Alioto, Massimo},
  biburl = {http://www.bibsonomy.org/bibtex/297f6878c79da0fd5c007eb25859741b8/dblp},
  ee = {http://dx.doi.org/10.1109/TVLSI.2013.2293135},
  interhash = {1c187b15902d39493dc3e87273f38334},
  intrahash = {97f6878c79da0fd5c007eb25859741b8},
  journal = {IEEE Trans. VLSI Syst.},
  keywords = {dblp},
  number = {12},
  pages = {2488-2498},
  title = {Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level.},
  url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#EsseniGKRA14},
  volume = {22},
  year = {2014}
}

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