Simulation of Memory Chip Line Using an Electronics Manufacturing Simulator. Estremadoyro, D. N., Farrington, P. A., Schroer, B. J., & Swain, J. J. In Andradóttir, S., Healy, K. J., Withers, D. H., & Nelson, B. L., editors, Winter Simulation Conference, pages 1330-1337, 1997. ACM. Link Paper bibtex @inproceedings{ conf/wsc/EstremadoyroFSS97,
added-at = {2014-12-15T00:00:00.000+0100},
author = {Estremadoyro, Douglas N. and Farrington, Phillip A. and Schroer, Bernard J. and Swain, James J.},
biburl = {http://www.bibsonomy.org/bibtex/21471c87c0add4b3e506e8bdff7840d26/dblp},
booktitle = {Winter Simulation Conference},
crossref = {conf/wsc/1997},
editor = {Andradóttir, Sigrún and Healy, Kevin J. and Withers, David H. and Nelson, Barry L.},
ee = {http://doi.acm.org/10.1145/268437.268779},
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isbn = {0-7803-4278-X},
keywords = {dblp},
pages = {1330-1337},
publisher = {ACM},
title = {Simulation of Memory Chip Line Using an Electronics Manufacturing Simulator.},
url = {http://dblp.uni-trier.de/db/conf/wsc/wsc1997.html#EstremadoyroFSS97},
year = {1997}
}
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