A 3.7mW, 1.6V CMOS analog adaptive equalizer for a 125Mbps wire-line transceiver. Fayed, A. & Ismail, M. In Proceedings - IEEE International Symposium on Circuits and Systems, 2007.
abstract   bibtex   
An analog adaptive equalizer based on feed-forward architecture is implemented on 0.18um digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125Mbps over UTP CAT-5 cable of up to 100m length. Novel low-voltage, low-power circuit techniques resulted in 3.7mW total power consumption and supply voltage operation as low as 1.6V. This is over 3x power savings and 0.4V reduction in supply voltage from previously reported implementations on the same process node. The minimum horizontal eye opening of the equalizer (including the transmit path driver) under all cable length is 0.67 UI and the total area of the equalizer is 27738 μm 2 . © 2007 IEEE.
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 title = {A 3.7mW, 1.6V CMOS analog adaptive equalizer for a 125Mbps wire-line transceiver},
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 year = {2007},
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 abstract = {An analog adaptive equalizer based on feed-forward architecture is implemented on 0.18um digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125Mbps over UTP CAT-5 cable of up to 100m length. Novel low-voltage, low-power circuit techniques resulted in 3.7mW total power consumption and supply voltage operation as low as 1.6V. This is over 3x power savings and 0.4V reduction in supply voltage from previously reported implementations on the same process node. The minimum horizontal eye opening of the equalizer (including the transmit path driver) under all cable length is 0.67 UI and the total area of the equalizer is 27738 μm  2 . © 2007 IEEE.},
 bibtype = {inProceedings},
 author = {Fayed, A. and Ismail, M.},
 booktitle = {Proceedings - IEEE International Symposium on Circuits and Systems}
}

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