A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables. Fayed, A. & Ismail, M. IEEE Transactions on Circuits and Systems I: Regular Papers, 2008.
abstract   bibtex   
An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-μ digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps over Unshielded-Twisted-Pair Category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 μ 2 . © 2008 IEEE.
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 title = {A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables},
 type = {article},
 year = {2008},
 identifiers = {[object Object]},
 keywords = {Adaptive equalizers,Adaptive filters,CMOS integrated circuits,Intersymbol interference (ISI),Transceivers},
 volume = {55},
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 abstract = {An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-μ digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps over Unshielded-Twisted-Pair Category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 μ  2 . © 2008 IEEE.},
 bibtype = {article},
 author = {Fayed, A.A. and Ismail, M.},
 journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
 number = {2}
}
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