NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices. Ferrer, D., González, R., Fleitas, R., Acle, J. P., & Canetti, R. In DATE, pages 218-223, 2004. IEEE Computer Society.  
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Paper  bibtex   @inproceedings{conf/date/FerrerGFAC04,
  added-at = {2015-11-11T00:00:00.000+0100},
  author = {Ferrer, Daniel and González, Ramiro and Fleitas, Roberto and Acle, Julio Pérez and Canetti, Rafael},
  biburl = {http://www.bibsonomy.org/bibtex/278a8c287cb3a3a5225c173e1bfff6eb8/dblp},
  booktitle = {DATE},
  crossref = {conf/date/2004},
  ee = {http://dl.acm.org/citation.cfm?id=969246},
  interhash = {4c2632f06f91138da486da5ef25fb430},
  intrahash = {78a8c287cb3a3a5225c173e1bfff6eb8},
  isbn = {0-7695-2085-5},
  keywords = {dblp},
  pages = {218-223},
  publisher = {IEEE Computer Society},
  timestamp = {2015-11-13T12:00:36.000+0100},
  title = {NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices.},
  url = {http://dblp.uni-trier.de/db/conf/date/date2004-df.html#FerrerGFAC04},
  year = 2004
} 
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