Address compression and heterogeneous interconnects for energy-efficient high-performance in tiled CMPs. Flores, A., Acacio, M., E., & Aragón, J., L. Proceedings of the International Conference on Parallel Processing, 2008.
abstract   bibtex   
Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance- and energy-efficient message management in tiled CMPs that combines both address compression with a heterogeneous interconnect. Our proposal consists of applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area can be exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the Energy-Delay2 Product of the interconnect. © 2008 IEEE.
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 title = {Address compression and heterogeneous interconnects for energy-efficient high-performance in tiled CMPs},
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 abstract = {Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance- and energy-efficient message management in tiled CMPs that combines both address compression with a heterogeneous interconnect. Our proposal consists of applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area can be exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the Energy-Delay2 Product of the interconnect. © 2008 IEEE.},
 bibtype = {article},
 author = {Flores, Antonio and Acacio, Manuel E. and Aragón, Juan L.},
 journal = {Proceedings of the International Conference on Parallel Processing}
}
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