An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. Flores, A., Aragón, J. L., & Acacio, M. E. J. Supercomput., 45(3):341–364, 2008.

Paper doi bibtex

@article{DBLP:journals/tjs/FloresAA08,
  author    = {Antonio Flores and
               Juan L. Arag{\'{o}}n and
               Manuel E. Acacio},
  title     = {An energy consumption characterization of on-chip interconnection
               networks for tiled {CMP} architectures},
  journal   = {J. Supercomput.},
  volume    = {45},
  number    = {3},
  pages     = {341--364},
  year      = {2008},
  url       = {https://doi.org/10.1007/s11227-008-0178-0},
  doi       = {10.1007/s11227-008-0178-0},
  timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/tjs/FloresAA08.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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