@inproceedings{conf/isscc/FujiwaraWCLSWLL15,
  added-at = {2015-03-24T00:00:00.000+0100},
  author = {Fujiwara, Hidehiro and Wang, Li-Wen and Chen, Yen-Huei and Lin, Kao-Cheng and Sun, Dar and Wu, Shin-Rung and Liaw, Jhon-Jhy and Lin, Chih-Yung and Chiang, Mu-Chi and Liao, Hung-Jen and Wu, Shien-Yang and Chang, Jonathan},
  biburl = {http://www.bibsonomy.org/bibtex/2a9a2f713aa938422e63e5d3c08e08869/dblp},
  booktitle = {ISSCC},
  crossref = {conf/isscc/2015},
  ee = {http://dx.doi.org/10.1109/ISSCC.2015.7063051},
  interhash = {ec2a5b8c161a6237ecbd0a5c696d525b},
  intrahash = {a9a2f713aa938422e63e5d3c08e08869},
  isbn = {978-1-4799-6224-2},
  keywords = {dblp},
  pages = {1-3},
  publisher = {IEEE},
  timestamp = {2015-06-18T16:09:38.000+0200},
  title = {17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.},
  url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2015.html#FujiwaraWCLSWLL15},
  year = 2015
}

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