Intel® XScale® Micro-Architecture. Furht, B., editor In Encyclopedia of Multimedia, pages 360–360. Springer US, 2008. 00000![Intel® XScale® Micro-Architecture [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper abstract bibtex DefinitionThe Intel XScale micro-architecture is an implementation of the ARM V5TE architecture.The XScale core supports both dynamic frequency and voltage scaling with a maximum frequency today in handheld devices of 624MHz (and increasing going forward). The design is a scalar, in-order single issue architecture with concurrent execution in three pipes that support out-of-order return. To support the frequency targets, a 7-stage integer pipeline is employed with dynamic branch prediction supplied to mitigate the cost of a deeper pipeline (see Fig. 1).Intel® XScale® Micro-Architecture. Figure 1.Pipelines applied in Intel XScale processor.In favor of memory access efficiency, the Intel XScale micro-architecture contains instruction and data caches (32KB each). Also, in order to hide memory latency the micro-architecture supports software issued prefetch capability coupled with advanced load and store buffering. Load buffering allows multiple data/cache lines request from the ...
@incollection{furht_intel_2008,
title = {Intel® {XScale}® {Micro}-{Architecture}},
copyright = {©2008 Springer-Verlag},
isbn = {978-0-387-74724-8 978-0-387-78414-4},
url = {http://link.springer.com/referenceworkentry/10.1007/978-0-387-78414-4_93},
abstract = {DefinitionThe Intel XScale micro-architecture is an implementation of the ARM V5TE architecture.The XScale core supports both dynamic frequency and voltage scaling with a maximum frequency today in handheld devices of 624MHz (and increasing going forward). The design is a scalar, in-order single issue architecture with concurrent execution in three pipes that support out-of-order return. To support the frequency targets, a 7-stage integer pipeline is employed with dynamic branch prediction supplied to mitigate the cost of a deeper pipeline (see Fig. 1).Intel® XScale® Micro-Architecture. Figure 1.Pipelines applied in Intel XScale processor.In favor of memory access efficiency, the Intel XScale micro-architecture contains instruction and data caches (32KB each). Also, in order to hide memory latency the micro-architecture supports software issued prefetch capability coupled with advanced load and store buffering. Load buffering allows multiple data/cache lines request from the ...},
language = {en},
urldate = {2016-05-03},
booktitle = {Encyclopedia of {Multimedia}},
publisher = {Springer US},
editor = {Furht, Borko},
year = {2008},
note = {00000},
pages = {360--360}
}
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