Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. Gaillardon, P., Amarù, L. G., Bobba, S., Marchi, M. D., Sacchetto, D., Leblebici, Y., & Micheli, G. D. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pages 625–630, 2013.
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/date/GaillardonABMSLM13,
  author    = {Pierre{-}Emmanuel Gaillardon and
               Luca Gaetano Amar{\`{u}} and
               Shashikanth Bobba and
               Michele De Marchi and
               Davide Sacchetto and
               Yusuf Leblebici and
               Giovanni De Micheli},
  title     = {Vertically-stacked double-gate nanowire FETs with controllable polarity:
               from devices to regular ASICs},
  booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
               March 18-22, 2013},
  pages     = {625--630},
  year      = {2013},
  crossref  = {DBLP:conf/date/2013},
  url       = {https://doi.org/10.7873/DATE.2013.137},
  doi       = {10.7873/DATE.2013.137},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/date/GaillardonABMSLM13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Downloads: 0