Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. Gaillardon, P., Ghasemzadeh, H., & Micheli, G. D. In 14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013, pages 1–6, 2013.
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/latw/GaillardonGM13,
  author    = {Pierre{-}Emmanuel Gaillardon and
               Hassan Ghasemzadeh and
               Giovanni De Micheli},
  title     = {Vertically-stacked silicon nanowire transistors with controllable
               polarity: {A} robustness study},
  booktitle = {14th Latin American Test Workshop, {LATW} 2013, Cordoba, Argentina,
               3-5 April, 2013},
  pages     = {1--6},
  year      = {2013},
  crossref  = {DBLP:conf/latw/2013},
  url       = {https://doi.org/10.1109/LATW.2013.6562673},
  doi       = {10.1109/LATW.2013.6562673},
  timestamp = {Wed, 16 Oct 2019 16:49:09 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/latw/GaillardonGM13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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