@article{journals/jsa/GarayODCA13,
  added-at = {2020-06-10T00:00:00.000+0200},
  author = {Garay, Godofredo R. and Lopera, Julio Ortega and Díaz, Antonio F. and Corrales, Luis and Aquino, Vicente Alarcón},
  biburl = {https://www.bibsonomy.org/bibtex/2b9c619e0b1eb4c5a5bcb53d1c14183d2/dblp},
  ee = {https://doi.org/10.1016/j.sysarc.2013.09.006},
  interhash = {cc2052c6b4bdf805934c97f7671fc273},
  intrahash = {b9c619e0b1eb4c5a5bcb53d1c14183d2},
  journal = {J. Syst. Archit.},
  keywords = {dblp},
  number = {10-D},
  pages = {1277-1298},
  timestamp = {2020-06-11T11:39:40.000+0200},
  title = {System performance evaluation by combining RTC and VHDL simulation: A case study on NICs.},
  url = {http://dblp.uni-trier.de/db/journals/jsa/jsa59.html#GarayODCA13},
  volume = 59,
  year = 2013
}

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