A low-power CT Incremental 3rd Order ΣΔ ADC for biosensor applications. Garcia, J., Rodriguez, S., & Rusu, A. IEEE Transactions on Circuits and Systems I: Regular Papers, 2013.
abstract   bibtex   
This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. © 2004-2012 IEEE.
@article{
 title = {A low-power CT Incremental 3rd Order ΣΔ ADC for biosensor applications},
 type = {article},
 year = {2013},
 identifiers = {[object Object]},
 keywords = {A/D conversion,continuous-time,incremental σδ ADC},
 volume = {60},
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 abstract = {This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. © 2004-2012 IEEE.},
 bibtype = {article},
 author = {Garcia, J. and Rodriguez, S. and Rusu, A.},
 journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
 number = {1}
}

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