Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations. Garg, L. & Sahula, V. IET Electronics Letters, 49(10):644-646, May, 2013. ![Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex Presented is the error that occurs while estimating subthreshold leakage power of parallel transistor stacks in CMOS gates using leakage power models when there is no consideration of the manufacturing variations, i.e. device geometry related effects in width. For the purpose, efficient support vector machine based macromodels for characterising the transistor stacks of CMOS gates are reported, considering process parameter variations impacting e.g. length, threshold voltage, oxide thickness, supply voltage, temperature and width of the transistors. The experiments show that maximum error can go up to 15% for AOI22 and OAI22 gate under nominal values of varying parameters without considering manufacturing variations in the width.
@Article{lokesh2013ecletter,
author = {Lokesh Garg and Vineet Sahula},
title = {Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations},
journal = {IET Electronics Letters},
year = {2013},
volume = {49},
number = {10},
pages = {644-646},
month = {May},
issn = {0013-5194},
doi = {10.1049/el.2012.4311},
url = {http://ieeexplore.ieee.org/document/6528801/},
abstract = {Presented is the error that occurs while estimating subthreshold leakage power of parallel transistor stacks in CMOS gates using leakage power models when there is no consideration of the manufacturing variations, i.e. device geometry related effects in width. For the purpose, efficient support vector machine based macromodels for characterising the transistor stacks of CMOS gates are reported, considering process parameter variations impacting e.g. length, threshold voltage, oxide thickness, supply voltage, temperature and width of the transistors. The experiments show that maximum error can go up to ~15% for AOI22 and OAI22 gate under nominal values of varying parameters without considering manufacturing variations in the width.},
keywords = {CMOS integrated circuits;electronic engineering computing;support vector machines;transistor circuits;CMOS gates;CMOS subthreshold leakage analysis;leakage power models;parallel transistor stacks;parameter variations;stack based models;support vector machine},
}
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