@Article{lokesh2016tcas2,
  author   = {Lokesh Garg and Vineet Sahula},
  title    = {Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits},
  journal  = {IEEE Transactions on Circuits and Systems II: Express Briefs},
  year     = {2016},
  volume   = {63},
  number   = {5},
  pages    = {468-472},
  month    = {05},
  issn     = {1549-7747},
  doi      = {10.1109/TCSII.2015.2504270},
  url      = {http://ieeexplore.ieee.org/document/7339471/},
  abstract = {Static virtual ground voltage (Vgnd) is an important parameter to be accurately and efficiently estimated for fine-grained power gating in logic circuits. Previous work results in a large error in Vgnd estimation due to conservative leakage models and inaccurate assumption of voltage conditions at the input of CMOS gates in power-gated circuits. To overcome these problems, we propose support vector machine (SVM)-based macromodels to estimate the leakage current of CMOS gates and thus achieve effective reduction in error in leakage model characterization. These models are then used in SVM classifier (SVC) and regressor to formulate an SVM regression-based Vgnd model. The SVC results in 3 times savings in data generation time compared with HSPICE simulation to develop the final Vgnd model. The proposed model results in <; 1% error and 23 000 times the speedup than HSPICE for the largest benchmark circuit.},
  keywords = {CMOS logic circuits;logic circuits;low-power electronics;regression analysis;support vector machines;CMOS gates;HSPICE simulation;SVC;SVM based macromodels;SVM classifier;SVM regression;Vgnd estimation;fine grained power gating;leakage model characterization;logic circuits;power gated circuits;static virtual ground voltage estimation macromodels;support vector machine based macromodels;CMOS integrated circuits;Integrated circuit modeling;Logic circuits;Logic gates;Semiconductor device modeling;Support vector machines;Transistors;Complimentary metal???oxide???semiconductor (CMOS) gates;Leakage current;Power gating;Support Vector Machine (SVM);leakage current;power gating;support vector machine (SVM);transistor stacks;virtual ground},
  owner    = {vinee},
}

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