@inProceedings{
 title = {Power analysis for Asynchronous CLICH Network-on-Chip},
 type = {inProceedings},
 year = {2010},
 identifiers = {[object Object]},
 keywords = {CLICH,GALS,Low Power,NoC},
 id = {e1062802-df2d-3a0b-8e3f-9d57d0909ba6},
 created = {2017-12-04T05:34:53.168Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:34:53.168Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICH) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches ( data  satisfies a certain condition. The area of Asynchronous CLICH switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the ( data  equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the ( data . The total metal resources required to implement Asynchronous design is decreased by 7%. © 2010 IEEE.},
 bibtype = {inProceedings},
 author = {Ghany, M.A.A.E. and Reehal, G. and Korzec, D. and Ismail, M.},
 booktitle = {Proceedings - IEEE International SOC Conference, SOCC 2010}
}

{"_id":"gpLuqrjF4i88GDeKs","bibbaseid":"ghany-reehal-korzec-ismail-poweranalysisforasynchronousclichnetworkonchip-2010","downloads":0,"creationDate":"2018-11-02T20:16:34.506Z","title":"Power analysis for Asynchronous CLICH Network-on-Chip","author_short":["Ghany, M.","Reehal, G.","Korzec, D.","Ismail, M."],"year":2010,"bibtype":"inProceedings","biburl":null,"bibdata":{"title":"Power analysis for Asynchronous CLICH Network-on-Chip","type":"inProceedings","year":"2010","identifiers":"[object Object]","keywords":"CLICH,GALS,Low Power,NoC","id":"e1062802-df2d-3a0b-8e3f-9d57d0909ba6","created":"2017-12-04T05:34:53.168Z","file_attached":false,"profile_id":"99d7e05e-a704-3549-ada2-dfc74a2d55ec","last_modified":"2017-12-04T05:34:53.168Z","read":false,"starred":false,"authored":"true","confirmed":false,"hidden":false,"private_publication":false,"abstract":"Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICH) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches ( data satisfies a certain condition. The area of Asynchronous CLICH switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the ( data equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the ( data . The total metal resources required to implement Asynchronous design is decreased by 7%. © 2010 IEEE.","bibtype":"inProceedings","author":"Ghany, M.A.A.E. and Reehal, G. and Korzec, D. and Ismail, M.","booktitle":"Proceedings - IEEE International SOC Conference, SOCC 2010","bibtex":"@inProceedings{\n title = {Power analysis for Asynchronous CLICH Network-on-Chip},\n type = {inProceedings},\n year = {2010},\n identifiers = {[object Object]},\n keywords = {CLICH,GALS,Low Power,NoC},\n id = {e1062802-df2d-3a0b-8e3f-9d57d0909ba6},\n created = {2017-12-04T05:34:53.168Z},\n file_attached = {false},\n profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},\n last_modified = {2017-12-04T05:34:53.168Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {false},\n hidden = {false},\n private_publication = {false},\n abstract = {Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICH) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches ( data satisfies a certain condition. The area of Asynchronous CLICH switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the ( data equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the ( data . The total metal resources required to implement Asynchronous design is decreased by 7%. © 2010 IEEE.},\n bibtype = {inProceedings},\n author = {Ghany, M.A.A.E. and Reehal, G. and Korzec, D. and Ismail, M.},\n booktitle = {Proceedings - IEEE International SOC Conference, SOCC 2010}\n}","author_short":["Ghany, M.","Reehal, G.","Korzec, D.","Ismail, M."],"bibbaseid":"ghany-reehal-korzec-ismail-poweranalysisforasynchronousclichnetworkonchip-2010","role":"author","urls":{},"keyword":["CLICH","GALS","Low Power","NoC"],"downloads":0,"html":""},"search_terms":["power","analysis","asynchronous","clich","network","chip","ghany","reehal","korzec","ismail"],"keywords":["clich","gals","low power","noc"],"authorIDs":[]}