Enhanced Multi-Core Performance Using Novel Thread Aware Cache Coherence and Prefetch-Control Mechanism. Ghosh, S. N., Sahula, V., & Bhargava, L. IEEE Embedded Systems Letters, 2022.
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Paper doi bibtex
Paper doi bibtex @Article{soma2022esl,
author = {Soma Niloy Ghosh and Vineet Sahula and Lava Bhargava},
journal = {IEEE Embedded Systems Letters},
title = {Enhanced Multi-Core Performance Using Novel Thread Aware Cache Coherence and Prefetch-Control Mechanism},
year = {2022},
doi = {https://doi.org/10.1109/LES.2022.3187418},
url = {https://ieeexplore.ieee.org/iel7/4563995/5170179/09811525.pdf},
}Downloads: 0
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