A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. Gierenz, V. S., Weiss, O., Noll, T. G., Carew, I., Ashley, J. J., & Karabed, R. In ASAP, pages 195-, 2000. IEEE Computer Society. Link Paper bibtex @inproceedings{conf/asap/GierenzWNCAK00,
added-at = {2015-12-03T00:00:00.000+0100},
author = {Gierenz, V. S. and Weiss, Oliver and Noll, Tobias G. and Carew, I. and Ashley, Jonathan J. and Karabed, Razmik},
biburl = {http://www.bibsonomy.org/bibtex/2672337fec70cc440605908e2910e5407/dblp},
booktitle = {ASAP},
crossref = {conf/asap/2000},
ee = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2000.862390},
interhash = {c880faf9ae5f1be8d9583ff9bcac2ac9},
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isbn = {0-7695-0716-6},
keywords = {dblp},
pages = {195-},
publisher = {IEEE Computer Society},
timestamp = {2015-12-04T11:40:43.000+0100},
title = {A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.},
url = {http://dblp.uni-trier.de/db/conf/asap/asap2000.html#GierenzWNCAK00},
year = 2000
}
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