BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. Girard, P., Héron, O., Pravossoudovitch, S., & Renovell, M. In Proceedings of International On-Line Testing Symposium (IOLTS), pages 187-192, 2004.

Paper bibtex

@inproceedings{ dblp3596802,
  title = {BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs},
  author = {Patrick Girard and Olivier Héron and Serge Pravossoudovitch and Michel Renovell},
  author_short = {Girard, P. and Héron, O. and Pravossoudovitch, S. and Renovell, M.},
  bibtype = {inproceedings},
  type = {inproceedings},
  year = {2004},
  key = {dblp3596802},
  id = {dblp3596802},
  biburl = {http://www.dblp.org/rec/bibtex/conf/iolts/GirardHPR04},
  url = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2004.17},
  conference = {IOLTS},
  pages = {187-192},
  text = {IOLTS 2004:187-192},
  booktitle = {Proceedings of International On-Line Testing Symposium (IOLTS)}
}

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