Low power BIST design by hypergraph partitioning: methodology and architectures. Girard, P., Landrault, C., Guiller, L., & Pravossoudovitch, S. In Proceedings of International Test Conference (ITC), pages 652-661, 2000.
Low power BIST design by hypergraph partitioning: methodology and architectures [link]Paper  bibtex   
@inproceedings{ dblp3940975,
  title = {Low power BIST design by hypergraph partitioning: methodology and architectures},
  author = {Patrick Girard and Christian Landrault and Loïs Guiller and Serge Pravossoudovitch},
  author_short = {Girard, P. and Landrault, C. and Guiller, L. and Pravossoudovitch, S.},
  bibtype = {inproceedings},
  type = {inproceedings},
  year = {2000},
  key = {dblp3940975},
  id = {dblp3940975},
  biburl = {http://www.dblp.org/rec/bibtex/conf/itc/GirardLGP00},
  url = {http://doi.ieeecomputersociety.org/10.1109/TEST.2000.894260},
  conference = {ITC},
  pages = {652-661},
  text = {ITC 2000:652-661},
  booktitle = {Proceedings of International Test Conference (ITC)}
}

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