High Defect Coverage with Low-Power Test Sequences in a BIST Environment. Girard, P., Landrault, C., Pravossoudovitch, S., Virazel, A., & Wunderlich, H. IEEE Design & Test of Computers (DT), 19(5):44-52, 2002.
High Defect Coverage with Low-Power Test Sequences in a BIST Environment [link]Paper  bibtex   
@article{ dblp3784103,
  title = {High Defect Coverage with Low-Power Test Sequences in a BIST Environment},
  author = {Patrick Girard and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel and Hans-Joachim Wunderlich},
  author_short = {Girard, P. and Landrault, C. and Pravossoudovitch, S. and Virazel, A. and Wunderlich, H.},
  bibtype = {article},
  type = {article},
  year = {2002},
  key = {dblp3784103},
  id = {dblp3784103},
  biburl = {http://www.dblp.org/rec/bibtex/journals/dt/GirardLPVW02},
  url = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.1033791},
  journal = {IEEE Design & Test of Computers (DT)},
  pages = {44-52},
  number = {5},
  volume = {19},
  text = {IEEE Design & Test of Computers (DT) 19(5):44-52 (2002)}
}

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