@article{journals/jsa/GuntherD00,
  added-at = {2020-05-19T00:00:00.000+0200},
  author = {Günther, Wolfgang and Drechsler, Rolf},
  biburl = {https://www.bibsonomy.org/bibtex/2387448cc5e255a1a387699dcf8c826f5/dblp},
  ee = {https://www.wikidata.org/entity/Q59243010},
  interhash = {93577e04f97ac4d0a8328c4df4b90333},
  intrahash = {387448cc5e255a1a387699dcf8c826f5},
  journal = {J. Syst. Archit.},
  keywords = {dblp},
  number = 14,
  pages = {1321-1334},
  timestamp = {2020-05-20T11:50:10.000+0200},
  title = {ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.},
  url = {http://dblp.uni-trier.de/db/journals/jsa/jsa46.html#GuntherD00},
  volume = 46,
  year = 2000
}

{"_id":"hWmuhYggy5R5eacT4","bibbaseid":"gnther-drechsler-actioncombininglogicsynthesisandtechnologymappingformuxbasedfpgas-2000","authorIDs":[],"author_short":["Günther, W.","Drechsler, R."],"bibdata":{"bibtype":"article","type":"article","added-at":"2020-05-19T00:00:00.000+0200","author":[{"propositions":[],"lastnames":["Günther"],"firstnames":["Wolfgang"],"suffixes":[]},{"propositions":[],"lastnames":["Drechsler"],"firstnames":["Rolf"],"suffixes":[]}],"biburl":"https://www.bibsonomy.org/bibtex/2387448cc5e255a1a387699dcf8c826f5/dblp","ee":"https://www.wikidata.org/entity/Q59243010","interhash":"93577e04f97ac4d0a8328c4df4b90333","intrahash":"387448cc5e255a1a387699dcf8c826f5","journal":"J. Syst. Archit.","keywords":"dblp","number":"14","pages":"1321-1334","timestamp":"2020-05-20T11:50:10.000+0200","title":"ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.","url":"http://dblp.uni-trier.de/db/journals/jsa/jsa46.html#GuntherD00","volume":"46","year":"2000","bibtex":"@article{journals/jsa/GuntherD00,\n added-at = {2020-05-19T00:00:00.000+0200},\n author = {Günther, Wolfgang and Drechsler, Rolf},\n biburl = {https://www.bibsonomy.org/bibtex/2387448cc5e255a1a387699dcf8c826f5/dblp},\n ee = {https://www.wikidata.org/entity/Q59243010},\n interhash = {93577e04f97ac4d0a8328c4df4b90333},\n intrahash = {387448cc5e255a1a387699dcf8c826f5},\n journal = {J. Syst. Archit.},\n keywords = {dblp},\n number = 14,\n pages = {1321-1334},\n timestamp = {2020-05-20T11:50:10.000+0200},\n title = {ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.},\n url = {http://dblp.uni-trier.de/db/journals/jsa/jsa46.html#GuntherD00},\n volume = 46,\n year = 2000\n}\n\n","author_short":["Günther, W.","Drechsler, R."],"key":"journals/jsa/GuntherD00","id":"journals/jsa/GuntherD00","bibbaseid":"gnther-drechsler-actioncombininglogicsynthesisandtechnologymappingformuxbasedfpgas-2000","role":"author","urls":{"Link":"https://www.wikidata.org/entity/Q59243010","Paper":"http://dblp.uni-trier.de/db/journals/jsa/jsa46.html#GuntherD00"},"keyword":["dblp"],"downloads":0},"bibtype":"article","biburl":"http://www.bibsonomy.org/bib/author/Gunther?items=1000","creationDate":"2020-11-19T14:18:48.590Z","downloads":0,"keywords":["dblp"],"search_terms":["action","combining","logic","synthesis","technology","mapping","mux","based","fpgas","günther","drechsler"],"title":"ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.","year":2000,"dataSources":["vx3tQbZepny2tNB7k"]}