A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V.

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V. Goll, B. & Zimmermann, H. IEEE Trans. on Circuits and Systems, 56-II(11):810-814, 2009.

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@article{ journals/tcas/GollZ09,
  added-at = {2012-05-09T00:00:00.000+0200},
  author = {Goll, Bernhard and Zimmermann, Horst},
  biburl = {http://www.bibsonomy.org/bibtex/277740de49c8951e993472cfdedd80db0/dblp},
  ee = {http://dx.doi.org/10.1109/TCSII.2009.2030357},
  interhash = {709a73396110ea758d68fe0ec4403c49},
  intrahash = {77740de49c8951e993472cfdedd80db0},
  journal = {IEEE Trans. on Circuits and Systems},
  keywords = {dblp},
  number = {11},
  pages = {810-814},
  title = {A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V.},
  url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII56.html#GollZ09},
  volume = {56-II},
  year = {2009}
}

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